Thursday, 1 September 2022
Subscribe to:
Posts (Atom)
Verilog Code for Universal Shift Register
Universal Shift Register module universalshift (clr,clk,sel,in,out); input clr,clk; input [1:0]sel; input [3:0]parin; output reg[3:0]out; ...
-
Gate Level Modelling module 4to2encoder(a,b); input [3:0]a; output [1:0]b; wire x0,x1,x2,x3; xor g1(x0,a[3],a[2]); not g2(x1,a[0]); not g3...
-
Gate Level Modelling module comparator(a,b,c,d,e); input a,b; output c,d,e; wire p,q,r,s; not g1(p,a); not g2(q,b); and g3(c,p,b); and g4(...
-
Full adder module fulladder(a,b,cin,s,cout); input a, b, cin; output s, cout; wire x,y,z; xor g1(x,a,b); and g2(y,a,b); and g3(z, x,cin); ...
