Verilog Code for Universal Shift Register

  Universal Shift Register module universalshift (clr,clk,sel,in,out); input clr,clk; input [1:0]sel; input [3:0]parin; output reg[3:0]out; ...

  • Verilog code for 4 to 2 Encoder
      Gate Level Modelling module 4to2encoder(a,b); input [3:0]a; output [1:0]b; wire x0,x1,x2,x3; xor g1(x0,a[3],a[2]); not g2(x1,a[0]); not g3...
  • Verilog code for SR Flipflop
      Gate Level Modelling module srflipflop(q,qbar,s,r,clk); input s,r,clk; output reg q,qbar; wire x,y; nand g1(x, s,clk); nand g2(y,r,clk); n...
  • Verilog Code for 8-Bit Ripple Carry Adder
      Full adder module fulladder(a,b,cin,s,cout); input a, b, cin; output s, cout; wire x,y,z; xor g1(x,a,b); and g2(y,a,b); and g3(z, x,cin); ...