Verilog code for 4 to 2 Encoder

 

Gate Level Modelling

module 4to2encoder(a,b);

input [3:0]a;

output [1:0]b;

wire x0,x1,x2,x3;

xor g1(x0,a[3],a[2]);

not g2(x1,a[0]);

not g3(x2,a[1]);

not g4(x3,a[2]);

and g5(b[1], x0, x1,x2);

xor g6(x4, a[3], a[1]);

and g7(b[0], x1, x3, x4);

endmodule

Data flow Level Modelling

module 4to2encoder(a,b);

input [3:0]a;

output [1:0]b;

assign b[1] = (a[3]^a[2]) & (~a[1]&~a[0]);

assign b[0] = (a[3]^a[1]) & (~a[2]&~a[0]);

endmodule

Behavioral Level Modelling

module 4to2encoder(a,b);

input [3:0]a;

output reg [1:0]b;

always @ (a)

case({a})

4'b0001: begin b[0] = 0; b[1] = 0; end

4'b0010: begin b[0] = 1; b[1] = 0; end

4'b0100: begin b[0] = 0; b[1] = 1; end

4'b1000: begin b[0] = 1; b[1] = 1; end

endcase

end

endmodule