Thursday, 24 March 2022
Wednesday, 2 February 2022
Verilog Code for 3 to 8 Decoder
Gate Level Modelling
module 3to8decoder(a,b,c, d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
wire w1,w2,w3;
not g1(w1,a);
not g2(w2,b);
not g3(w3,c);
and g4(d0, w1,w2,w3);
and g5(d1, a,w2,w3);
and g6(d2,w1,b,w3);
and g6(d3, a,b,w3);
and g7(d4,w1,w2,c);
and g8(d5,a,w2,c);
and g9(d6,w1,b,c);
and g10(d7,a,b,c);
endmodule
Data Flow Level Modelling
module 3to8decoder(a,b,c, d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0 = ~a&~b&~c;
assign d1 = a&~b&~c;
assign d2 = ~a&b&~c;
assign d3 = a &b &c;
assign d4 = ~a&~b&c;
assign d5 = a&~b&c;
assign d6 = ~a&b&c;
assign d7 = a&b&c;
endmodule
Behavioral Level Modelling
module 3to8decoder(a,b,c, d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
always @ (a,b,c)
begin
case ({a,b,c})
begin
3'b000: d0=1; d1=0; d2=0; d3=0; d4=0;d5=0; d6=0; d7=0; end
3'b001: d0=0;d1=1;d2=0;d3=0;d4=0; d5=0; d6=0; d7=0; end
3'b010: d0=0;d1=0;d2=1;d3=0;d4=0; d5=0; d6=0; d7=0; end
3'b011: d0=0; d1=0; d2=0; d3=1; d4 = 0; d5=0; d6=0; d7=0; end
3'b100: d0=0; d1=0; d2=0; d3=0; d4=1; d5=0; d6=0; d7=0; end
3'b101: d0=0;d1=0;d2=0;d3=0;d4=0; d5=1; d6=0; d7=0; end
3'b110: d0=0;d1=0;d2=0;d3=0;d4 = 0;d5 = 0;d6=1;d7=0; end
3'b111: d0=0;d1=0;d2=0;d3=0;d4 = 0;d5 = 0;d6=0;d7=1;end
endcase
end
endmodule
Verilog Code for Universal Shift Register
Universal Shift Register module universalshift (clr,clk,sel,in,out); input clr,clk; input [1:0]sel; input [3:0]parin; output reg[3:0]out; ...
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Universal Shift Register module universalshift (clr,clk,sel,in,out); input clr,clk; input [1:0]sel; input [3:0]parin; output reg[3:0]out; ... -
Gate Level Modelling module 4to2encoder(a,b); input [3:0]a; output [1:0]b; wire x0,x1,x2,x3; xor g1(x0,a[3],a[2]); not g2(x1,a[0]); not g3...
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Gate Level Modelling module 2to4decoder(a0,a1, d0,d1,d2,d3); input a0,a1; output d0,d1,d2,d3; wire s,t; not g1(s,a0); not g2(t,a1); and g3...
