Verilog Code for magintude comparator

 

Gate Level Modelling

module comparator(a,b,c,d,e);

input a,b;

output c,d,e;

wire p,q,r,s;

not g1(p,a);

not g2(q,b);

and g3(c,p,b);

and g4(r, p,q);

and g5(s, a,b);

or g6(d, r,s);

and g7(e, a,q);

endmodule

Data Flow Level Modelling

module comparator(a,b,c,d,e);

input a,b;

output c,d,e;

assign c = ~a &b;

assign d = (~a&~b)|(a&b);

assign e = a&~b;

endmodule

Behavioral Level Modelling

module comparator(a,b,c,d,e);

input a,b;

output reg c,d,e;

always @(a,b)

begin

case({b,a})

2'b00: begin c = 0; d=1; e=0;end

2'b01: begin c = 0; d=0; e=1;end

2'b10: begin c = 1; d=0; e=0;end

2'b11:begin c = 0; d=1; e=0;end

endcase

end

endmodule