Verilog code for 2:1 MUX

 

Gate Level Modelling

module 2to1mux(y,s,D0,D1);

input D0,D1,s;

output y;

wire sbar,p,q;

not g1(sbar,s);

and g2(p,s,D1);

and g3(q,sbar,D0);

or g4(y,p,q);

endmodule

Data flow Level Modelling

module 2to1mux(y,s,D0,D1);

input D0,D1,s;

output y;

assign y = (D0&~s) | (D1&s);

endmodule

Behavioral Level Modelling

module 2to1mux(y,s,D0,D1);

input D0,D1,s;

output reg y;

always @( Do,D1,s)

begin

case({s})

1'b0: begin y = D0; end

1'b1: begin y = D1; end

endcase

end

endmodule