Verilog code for T Flipflop

 

Gate Level Modelling

module tflipflop(t,clk,q,qbar);

input t,clk;

output reg q,qbar;

wire x,y;

nand g1(x,t,clk,qbar);

nand g2(y,t,clk,q);

nand g3(q,x,qbar);

nand g4(qbar,y,q);

endmodule

Behavioral Level Modelling

module tflipflop(t,clk,q,qbar);

input t,clk;

output reg q,qbar;

always @ (posedge clk)

begin

case({t})

1'b0: begin q<=q; end

1'b1: begin q<=~q; end

endcase

end

endmodule