Verilog code for D Flipflop

 

Gate Level Modelling

module dflipflop(q,qbar,d,clk);

input d, clk;

output reg q,qbar;

wire x,y,z;

not g1(x,d);

nand g2(y, d, clk);

nand g3(z,x,clk);

nand g4(q,y,qbar);

nand g5(qbar, z, q);

endmodule

Behavioral Level Modelling

module dflipflop(q,qbar,d,clk);

input d, clk;

output reg q,qbar;

always@(posedge clk)

begin

case({d})

1'b0: begin q<=0; qbar <= 1; end

1'b1: begin q<=1; qbar <= 0; end

endcase

end

endmodule