Verilog Code for 4 to 2 Priority Encoder

 

Gate Level Modelling

module 4to2priorityencoder(y0,y1,y2,y3,a0,a1);

input y0,y1,y2,y3;

output a0,a1;

wire x0,x1;

not g1(x0,y2);

or g2(a1,y3,y2);

and g3(x1, x0,y1);

or g4(a0, x1, y3);

endmodule

Data Flow Level Modelling

module 4to2priorityencoder(y0,y1,y2,y3,a0,a1);

input y0,y1,y2,y3;

output a0,a1;

assign a1 = y3| y2;

assign a0 = (~y2 & y1) | y3;

endmodule

Behavioral Level Modelling

module 4to2priorityencoder(y0,y1,y2,y3,a0,a1);

input y0,y1,y2,y3;

output reg a0,a1;

always @(y)

begin

case({y3,y2,y1,y0})

4'b0001: begin a0=0; a1 = 0; end

4'b001x: begin a0=1; a1 = 0; end

4'b01xx: begin a0=0; a1 = 1; end

4'b1xxx: begin a0=1; a1 = 1; end

endcase

end

endmodule