Verilog Code for Carry Lookahead Adder

 

Gate Level Modelling

module carrylookahead(a,b,cin,sum,cout);

input a0,a1,a2,a3,b0,b1,b2,b3;

input cin;

output sum0,sum1,sum2,sum3;

output cout;

wire p0,p1,p2,p3,g0,g1,g2,g3,x0,x1,x2,x3;

wire c1,c2,c3;

xor g1(p0,a0,b0);

xor g2(p1,a1,b1);

xor g3(p2,a2,b2);

xor g4(p3,a3,b3);

and g5(g0, a0,b0);

and g6(g1, a1,b1);

and g7(g2, a2,b2);

and g8(g3,a3,b3);

and g9(x0, p0,cin);

and g10(x1, p1, c1);

and g11(x2, p2, c2);

and g12(x3, p3, c3);

xor g13(s0, p0,cin);

xor g14(s1, p1, c1);

xor g15(s2, p2, c2);

xor g16(s3, p3, c3);

or g17(c1,g0,x0);

or g18(c2, g1, x1);

or g19(c3,g2,x2);

or g20(cout, g3,x3);

endmodule

Data Flow Level Modelling

module carrylookahead(a,b,cin,sum,cout);

input a0,a1,a2,a3,b0,b1,b2,b3;

input cin;

output sum0,sum1,sum2,sum3;

output cout;

wire p0,p1,p2,p3,g0,g1,g2,g3,x0,x1,x2,x3;

wire c1,c2,c3;

p0 = a0^b0;

p1 = a1^b1;

p2 = a2^b2;

p3 = a3^b3;

g0 = a0&b0;

g1 = a1&b1;

g2 = a2&b2;

g3 = a3&b3;

c1 = go|(po&cin);

c2 = g1|(p1&c1);

c3 = go|(p2&c2);

cout = go|(p3&c3);

sum0 = p0^cin;

sum1 = p1^c1;

sum2 = p2^c2;

sum3 = p3^c3;

endmodule