Verilog Code for Demux

 

Gate Level Modelling

module demux(a1,a0, Din, y3,y2,y1,y0);

input a1,a0,Din;

output y3,y2,y1,y0;

wire s,t;

not g1(s,a0);

not g2(t,a1);

and g3(y0, s,t,Din);

and g4(y1, t, a0, Din);

and g5(y2, a1, s, Din);

and g6(y3, a0, a1, Din);

endmodule

Data flow Level Modelling

module demux(a1, a0, Din, y3, y2, y1, y0);

input a1, a0, Din;

output y3, y2, y1, y0;

assign y0 = ~a0 &~a1 & Din;

assign y1 = a0 & ~a1 & Din;

assign y2 = ~a0 & a1 & Din;

assign y3 = a0 & a1 & Din;

endmodule

Behavioral Level Modelling

module demux(a1, a0, Din, y3, y2, y1, y0);

input a1, a0, Din;

output reg y3, y2, y1, y0;

always @ (a0,a1,Din)

begin

case({a1,a0})

2'b00: begin y3 = Din; y2 = 0; y1 = 0; y0= 0; end

2'b01: begin y3 = 0; y2 = Din; y1 = 0; y0= 0; end

2'b01: begin y3 = 0; y2 = 0; y1 = Din; y0= 0; end

2'b01: begin y3 = 0; y2 = 0; y1 = 0; y0= Din; end

endcase

end

endmodule