Verilog Code for 8-Bit Ripple Carry Adder

 

Full adder

module fulladder(a,b,cin,s,cout);

input a, b, cin;

output s, cout;

wire x,y,z;

xor g1(x,a,b);

and g2(y,a,b);

and g3(z, x,cin);

xor g4(s, x,cin);

or g5(cout, y, z);

endmodule

8-bit Ripple carry adder using Full adder

module ripplecarryadder(a,b,c,sum,cout);

input [7:0]a,b;

input cin;

output reg [7:0]sum;

output cout;

wire [6:0]c;

fulladder f1(a[0],b[0],cin,sum[0],c[0]);

fulladder f2(a[1],b[1],c[0],sum[1],c[1]);

fulladder f3(a[2],b[2],c[1],sum[2],c[2]);

fulladder f4(a[3],b[3],c[2],sum[3],c[3]);

fulladder f1(a[4],b[4],c[3],sum[4],c[4]);

fulladder f2(a[5],b[5],c[4],sum[5],c[5]);

fulladder f3(a[6],b[6],c[5],sum[6],c[6]);

fulladder f4(a[7],b[7],c[6],sum[7],cout);

endmodule