Verilog code for Arithmetic and Logic Unit

 

Behavioral Level Modelling

module alu(s,a,b,f);

input[2:0]s;

input[3:0]a,b;

output[3:0]f;

reg[3:0]f;

always@(s or a or b)

begin

case(s)

3'b000:f<=4'b0000;

3'b001:f<=a-b;

3'b010:f<=a+b;

3'b011:f<=b-a;

3'b100:f<=a&b;

3'b101:f<=a|b;

3'b110:f<=~a;

default:f<=4'b1111;

endcase

end

endmodule