Verilog Code for 4 bit - Memory Unit

4 Bit - Memory Unit

module memory(RW, Datain, Dataout, CE, Address)

input CE, RW;

input [7:0] Address;

input [3:0] Datain;

Output [3:0] Dataout;

reg [3:0] Dataout;

reg [3:0] mem[127:0];

always @(CE or RW or Datain or Dataout or Address)

if(CE)

begin

if(RW)

Dataout = Mem[Address];

else

Mem[Address] = Datain;

else

Dataout = 4'bz;

end

endmodule