clc; clear all; clf;
t=[0:0.01:4.4*%pi];
A=5;
wc=5;
Vm=A.*squarewave(t);
Vc=A.*cos(wc.*t);
fc=wc/(2*%pi);
subplot(3,1,1);
plot(t,Vm, 'red');
xlabel("Time")
ylabel("Amplitude of Message Signal")
subplot(3,1,2);
plot(t,Vc, 'green');
xlabel("Time")
ylabel("Amplitude of Carrier Signal")
fd=0.5; //frequency deviation
subplot(3,1,3);
Vf=A.*cos(2.*%pi.*(fc+Vm.*fd).*t);
plot(t,Vf, 'blue');
xlabel("Time")
ylabel("Amplitude of FSK Signal")
Wednesday 9 November 2022
Communication Systems - FSK
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Verilog Code for Universal Shift Register
Universal Shift Register module universalshift (clr,clk,sel,in,out); input clr,clk; input [1:0]sel; input [3:0]parin; output reg[3:0]out; ...
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Full adder module fulladder(a,b,cin,s,cout); input a, b, cin; output s, cout; wire x,y,z; xor g1(x,a,b); and g2(y,a,b); and g3(z, x,cin); ...
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Universal Shift Register module universalshift (clr,clk,sel,in,out); input clr,clk; input [1:0]sel; input [3:0]parin; output reg[3:0]out; ...
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