Verilog Code for Half Adder

Gate Level Modelling

module Halfadder(a,b,s,c);

input a,b; 

output s,c; 

xor g1(s,a,b); 

and g2(c,a,b);

endmodule

Data Flow Level Modelling 

module Halfadder(a,b,s,c); 

input a,b; 

output s,c; 

assign s = a ^ b; 

assign c = a & b; 

endmodule 

Behavioural Flow Level Modelling 

module Halfadder(a,b,s,c); 

input a,b; 

output s,c; 

always @(a or b) 

begin 

case ({a,b}) 

2'b00: begin s = 0; c = 0; end  

2'b01: begin s = 1; c = 0; end 

2'b10: begin s = 1; c = 0; end 

2'b11: begin s = 0; c = 1; end 

endcase 

end 

endmodule