Verilog code for Full Adder

Sum = a^b^Cin

carry = ab | bc | ac

Gate Level Modelling

module fulladder(a,b,cin,s,cout);

input a, b, cin;

output s, cout;

wire x,y,z;

xor g1(x,a,b);

and g2(y,a,b);

and g3(z, x,cin);

xor g4(s, x,cin);

or g5(cout, y, z);

endmodule

Data flow modelling

module fulladder(a,b,cin,s,cout);

input a, b, cin;

output s, cout;

assign s= a^b^cin;

assign cout = (a&b) | (cin&a) | (cin&b);

endmodule

Behavioral level Modelling

module fulladder(a,b,cin,s,cout);

input a, b, cin;

output reg s, cout;

always @(a or b or cin)

begin

case ({a,b,cin})

3'b000: begin s= 0; cout=0; end

3'b001: begin s= 1; cout=0; end

3'b010: begin s= 1; cout=0; end

3'b011: begin s= 0; cout=1; end

3'b100: begin s= 1; cout=0; end

3'b101: begin s= 0; cout=1; end

3'b110: begin s= 0; cout=1; end

3'b111: begin s= 1; cout=1; end

end case

end

endmodule