Verilog code for Half Subtractor

 Diff= a^b

Borrow = (~a)b

Gate level Modelling

module halfsubtractor(d,b,x,y);

input x,y;

output d,b;

wire z;

xor g1(b,x,y);

not g2(z,x);

and g3(d,z,y);

endmodule

Data Flow Modelling

module halfsubtractor(d,b,x,y);

input x,y;

output d,b;

assign b= x^y;

assign d = ~x&y;

endmodule

Behavioral Level Modelling

module halfsubtractor(d,b,x,y);

input x,y;

output reg d,b;

always @(x,y)

begin

case({x,y})

2'b00: begin d= 0; b=0; end

2'b01: begin d= 1; b=1; end

2'b10: begin d= 1; b=0; end

2'b11: begin d= 0; b=0; end

endcase

end

endmodule