Verilog code for Full Subtractor

Diff = a^b^c

Borrow = (~(a ^ b) & c) | ((~a )& b)

 

Gate Level Modelling

module fullsubtractor(d,b,x,y,z);

input x,y,z;

output d,b;

wire p, q, r, s, t;

xor g1(p, x,y);

xor g2 (d,p,z);

not g3(q,x);

and g4(r, q,y);

not g5(s,p);

and g6(t,s,z);

or g7(b, t, r);

endmodule

Data Flow Level Modelling

module fullsubtractor(d,b,x,y,z);

input x,y,z;

output d,b;

assign d = x^y^z;

assign b = (~(x ^ y) & z) | (~x & y);

endmodule

Behavioral Level Modelling

module fullsubtractor(d,b,x,y,z);

input x,y,z;

output reg d,b;

always @ (x,y,z)

begin

case({x,y,z})

3'b000: begin d = 0; b= 0; end

3'b001: begin d = 1; b= 1; end

3'b010: begin d = 1; b= 1; end

3'b011: begin d = 0; b= 1; end

3'b100: begin d = 1; b= 0; end

3'b101: begin d = 0; b= 0; end

3'b110: begin d = 0; b= 0; end

3'b111: begin d = 1; b= 1; end

endcase

end

endmodule