Verilog Code for JK Flipflop

 

Gate Level Modelling

module jkflipflop(j,k,clk,q, qbar)

input j,k,clk;

output reg q,qbar;

wire x,y;

nand g1(x, j, qbar, clk);

nand g2(y, k, q, clk);

nand g3(q, qbar, x);

nand g4(qbar,q,y);

endmodule

Behavioral Level Modelling

module jkflipflop(j,k,clk,q)

input j,k,clk;

output reg q;

always @(posedge clk)

begin

case({j,k})

2'b00: begin q<=q; end

2'b01: begin q<=1; end

2'b10: begin q<=0; end

2'b11: begin q<=~q; end

endcase

end

endmodule