Verilog Code for Carry Lookahead Adder

 

Gate Level Modelling

module carrylookahead(a,b,cin,sum,cout);

input a0,a1,a2,a3,b0,b1,b2,b3;

input cin;

output sum0,sum1,sum2,sum3;

output cout;

wire p0,p1,p2,p3,g0,g1,g2,g3,x0,x1,x2,x3;

wire c1,c2,c3;

xor g1(p0,a0,b0);

xor g2(p1,a1,b1);

xor g3(p2,a2,b2);

xor g4(p3,a3,b3);

and g5(g0, a0,b0);

and g6(g1, a1,b1);

and g7(g2, a2,b2);

and g8(g3,a3,b3);

and g9(x0, p0,cin);

and g10(x1, p1, c1);

and g11(x2, p2, c2);

and g12(x3, p3, c3);

xor g13(s0, p0,cin);

xor g14(s1, p1, c1);

xor g15(s2, p2, c2);

xor g16(s3, p3, c3);

or g17(c1,g0,x0);

or g18(c2, g1, x1);

or g19(c3,g2,x2);

or g20(cout, g3,x3);

endmodule

Data Flow Level Modelling

module carrylookahead(a,b,cin,sum,cout);

input a0,a1,a2,a3,b0,b1,b2,b3;

input cin;

output sum0,sum1,sum2,sum3;

output cout;

wire p0,p1,p2,p3,g0,g1,g2,g3,x0,x1,x2,x3;

wire c1,c2,c3;

p0 = a0^b0;

p1 = a1^b1;

p2 = a2^b2;

p3 = a3^b3;

g0 = a0&b0;

g1 = a1&b1;

g2 = a2&b2;

g3 = a3&b3;

c1 = go|(po&cin);

c2 = g1|(p1&c1);

c3 = go|(p2&c2);

cout = go|(p3&c3);

sum0 = p0^cin;

sum1 = p1^c1;

sum2 = p2^c2;

sum3 = p3^c3;

endmodule

Verilog Code for 4 to 2 Priority Encoder

 

Gate Level Modelling

module 4to2priorityencoder(y0,y1,y2,y3,a0,a1);

input y0,y1,y2,y3;

output a0,a1;

wire x0,x1;

not g1(x0,y2);

or g2(a1,y3,y2);

and g3(x1, x0,y1);

or g4(a0, x1, y3);

endmodule

Data Flow Level Modelling

module 4to2priorityencoder(y0,y1,y2,y3,a0,a1);

input y0,y1,y2,y3;

output a0,a1;

assign a1 = y3| y2;

assign a0 = (~y2 & y1) | y3;

endmodule

Behavioral Level Modelling

module 4to2priorityencoder(y0,y1,y2,y3,a0,a1);

input y0,y1,y2,y3;

output reg a0,a1;

always @(y)

begin

case({y3,y2,y1,y0})

4'b0001: begin a0=0; a1 = 0; end

4'b001x: begin a0=1; a1 = 0; end

4'b01xx: begin a0=0; a1 = 1; end

4'b1xxx: begin a0=1; a1 = 1; end

endcase

end

endmodule

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Verilog code for 4 to 2 Encoder

 

Gate Level Modelling

module 4to2encoder(a,b);

input [3:0]a;

output [1:0]b;

wire x0,x1,x2,x3;

xor g1(x0,a[3],a[2]);

not g2(x1,a[0]);

not g3(x2,a[1]);

not g4(x3,a[2]);

and g5(b[1], x0, x1,x2);

xor g6(x4, a[3], a[1]);

and g7(b[0], x1, x3, x4);

endmodule

Data flow Level Modelling

module 4to2encoder(a,b);

input [3:0]a;

output [1:0]b;

assign b[1] = (a[3]^a[2]) & (~a[1]&~a[0]);

assign b[0] = (a[3]^a[1]) & (~a[2]&~a[0]);

endmodule

Behavioral Level Modelling

module 4to2encoder(a,b);

input [3:0]a;

output reg [1:0]b;

always @ (a)

case({a})

4'b0001: begin b[0] = 0; b[1] = 0; end

4'b0010: begin b[0] = 1; b[1] = 0; end

4'b0100: begin b[0] = 0; b[1] = 1; end

4'b1000: begin b[0] = 1; b[1] = 1; end

endcase

end

endmodule

Verilog code for 4-bit Ripple Carry Adder

 

Full adder

module fulladder(a,b,cin,s,cout);

input a, b, cin;

output s, cout;

wire x,y,z;

xor g1(x,a,b);

and g2(y,a,b);

and g3(z, x,cin);

xor g4(s, x,cin);

or g5(cout, y, z);

endmodule

4-bit Ripple carry adder using Full adder

module ripplecarryadder(a,b,c,sum,cout);

input [3:0]a,b;

input cin;

output reg [3:0]sum;

output cout;

wire [2:0]c;

fulladder f1(a[0],b[0],cin,sum[0],c[0]);

fulladder f2(a[1],b[1],c[0],sum[1],c[1]);

fulladder f3(a[2],b[2],c[1],sum[2],c[2]);

fulladder f4(a[3],b[3],c[2],sum[3],cout);

endmodule

Verilog Code for magintude comparator

 

Gate Level Modelling

module comparator(a,b,c,d,e);

input a,b;

output c,d,e;

wire p,q,r,s;

not g1(p,a);

not g2(q,b);

and g3(c,p,b);

and g4(r, p,q);

and g5(s, a,b);

or g6(d, r,s);

and g7(e, a,q);

endmodule

Data Flow Level Modelling

module comparator(a,b,c,d,e);

input a,b;

output c,d,e;

assign c = ~a &b;

assign d = (~a&~b)|(a&b);

assign e = a&~b;

endmodule

Behavioral Level Modelling

module comparator(a,b,c,d,e);

input a,b;

output reg c,d,e;

always @(a,b)

begin

case({b,a})

2'b00: begin c = 0; d=1; e=0;end

2'b01: begin c = 0; d=0; e=1;end

2'b10: begin c = 1; d=0; e=0;end

2'b11:begin c = 0; d=1; e=0;end

endcase

end

endmodule