clc; clear all; clf;
t=[0:0.01:4.4*%pi];
A=5;
wc=5;
Vm=A.*squarewave(t);
Vc=A.*cos(wc.*t);
fc=wc/(2*%pi);
subplot(3,1,1);
plot(t,Vm, 'red');
xlabel("Time")
ylabel("Amplitude of Message Signal")
subplot(3,1,2);
plot(t,Vc, 'green');
xlabel("Time")
ylabel("Amplitude of Carrier Signal")
fd=0.5; //frequency deviation
subplot(3,1,3);
Vf=A.*cos(2.*%pi.*(fc+Vm.*fd).*t);
plot(t,Vf, 'blue');
xlabel("Time")
ylabel("Amplitude of FSK Signal")
Wednesday, 9 November 2022
Communication Systems - FSK
Thursday, 1 September 2022
Thursday, 24 March 2022
Verilog Code for 4 bit - Memory Unit
4 Bit - Memory Unit
module memory(RW, Datain, Dataout, CE, Address)
input CE, RW;
input [7:0] Address;
input [3:0] Datain;
Output [3:0] Dataout;
reg [3:0] Dataout;
reg [3:0] mem[127:0];
always @(CE or RW or Datain or Dataout or Address)
if(CE)
begin
if(RW)
Dataout = Mem[Address];
else
Mem[Address] = Datain;
else
Dataout = 4'bz;
end
endmodule
Verilog Code for 8-Bit Ripple Carry Adder
Full adder
module fulladder(a,b,cin,s,cout);
input a, b, cin;
output s, cout;
wire x,y,z;
xor g1(x,a,b);
and g2(y,a,b);
and g3(z, x,cin);
xor g4(s, x,cin);
or g5(cout, y, z);
endmodule
8-bit Ripple carry adder using Full adder
module ripplecarryadder(a,b,c,sum,cout);
input [7:0]a,b;
input cin;
output reg [7:0]sum;
output cout;
wire [6:0]c;
fulladder f1(a[0],b[0],cin,sum[0],c[0]);
fulladder f2(a[1],b[1],c[0],sum[1],c[1]);
fulladder f3(a[2],b[2],c[1],sum[2],c[2]);
fulladder f4(a[3],b[3],c[2],sum[3],c[3]);
fulladder f1(a[4],b[4],c[3],sum[4],c[4]);
fulladder f2(a[5],b[5],c[4],sum[5],c[5]);
fulladder f3(a[6],b[6],c[5],sum[6],c[6]);
fulladder f4(a[7],b[7],c[6],sum[7],cout);
endmodule
Verilog code for Arithmetic and Logic Unit
Behavioral Level Modelling
module alu(s,a,b,f);
input[2:0]s;
input[3:0]a,b;
output[3:0]f;
reg[3:0]f;
always@(s or a or b)
begin
case(s)
3'b000:f<=4'b0000;
3'b001:f<=a-b;
3'b010:f<=a+b;
3'b011:f<=b-a;
3'b100:f<=a&b;
3'b101:f<=a|b;
3'b110:f<=~a;
default:f<=4'b1111;
endcase
end
endmodule
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Verilog Code for Universal Shift Register
Universal Shift Register module universalshift (clr,clk,sel,in,out); input clr,clk; input [1:0]sel; input [3:0]parin; output reg[3:0]out; ...
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Universal Shift Register module universalshift (clr,clk,sel,in,out); input clr,clk; input [1:0]sel; input [3:0]parin; output reg[3:0]out; ... -
Gate Level Modelling module 4to2encoder(a,b); input [3:0]a; output [1:0]b; wire x0,x1,x2,x3; xor g1(x0,a[3],a[2]); not g2(x1,a[0]); not g3...
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Gate Level Modelling module 2to4decoder(a0,a1, d0,d1,d2,d3); input a0,a1; output d0,d1,d2,d3; wire s,t; not g1(s,a0); not g2(t,a1); and g3...
